1. Field of the Invention
The present invention relates to an electronic component package and fabrication method thereof, and in particular relates to a stacked electronic component package and fabrication method thereof.
2. Description of the Related Art
Due to demand for miniaturized, lightweight and powerful electronic products, stacked electronic component packages have been disclosed. For a conventional chip scale package (CSP) using wire bonding technology, semiconductor chips are electrically connected to the lead outside of the package using bonding wires. Thus, for a stacked chip scale package (SCSP), the size of an upper level semiconductor chip is required to be larger or smaller than that of a lower level semiconductor chip. Therefore, miniaturization is hindered. While the total thickness of an SCSP may be reduced by a chip grinding process, the required chip grinding process increases chip packaging complexity and wire bonding difficulties along with broken chips, thus increasing costs. Additionally, since the size of the upper level semiconductor chip is larger than that of the lower level semiconductor chip, an overhang problem occurs, causing the upper level semiconductor chip to vibrate during the wire bonding process. Therefore, feasibly increasing the number of layers of an SCSP by conventional methods is not available, making stacked electronic component packages unable to meet further demands for even more miniaturized, lightweight and powerful electronic products.
Thus, a novel stacked electronic component package and fabricating method thereof having large numbers of stacked chips, high fabrication yield and low fabrication costs are desired.